The fabrication of integrated circuits is typically done by building successive layers on top of each other. These layers are built on or in an underlying substrate, such as single crystal silicon or an electrical insulator. When the substrate is an electrical insulator, such as sapphire, the fabrication techniques and resulting devices are often referred to as “silicon on insulator” or “semiconductor on insulator”, which are collectively called “SOI”.
Many process steps are typically involved in semiconductor fabrication including deposition, oxidation, planarization, etching, diffusion, implantation, and lithography. Lithography is used to form a desired pattern onto a surface. Conventional lithography typically uses a mask and photosensitive material known as “photoresist” to create the desired pattern. These fabrication techniques, however, have many variations and have applications in fields other than semiconductors. For example, lithography may be used in many different ways, such as with or without photoresist, with or without masks, and in fabricating technologies such as semiconductors, liquid crystal displays, micro-electromechanical systems, and others.
The continuous and significant advances in the semiconductor industry have been due, in part, to many technical advances, such as improved lenses, improved photoresist materials, improved chemical-mechanical polishing, and others. In the field of lithography, for example, advances have been made with the use of increasingly shorter wavelengths in the lithographic process. In general, shorter wavelengths provide better resolution but are more expensive to implement and they create other problems. Furthermore, physical limitations are presenting problems for the continued reduction in wavelengths in lithography.
Several solutions are being investigated for continued performance advances in semiconductor fabrication, such as electron projection lithography, immersion lithography, and extreme ultraviolet lithography. However, the proposed solutions require significant advances in technology, such as light sources, resist materials, masks, and process controls. Furthermore, the costs of lithography and other fabrication processes and tools have increased dramatically, and the research and development required for significant advances in various technologies will add to the costs.
There are also other problems with prior art integrated circuit technology. For example, the design processes, the lithographic masks, and the lithographic processes involved in prior art integrated circuit design and fabrication are complex and expensive. In addition, the utilization of integrated circuit area by active devices is relatively low. As a result, prior art integrated circuit designs and processes are expensive and result in inefficient utilization of resources.
A specific example of shortcomings in the prior art can be seen in conventional flash memory devices. Those devices suffer a significant voltage drop between the controlling gate and the bulk semiconductor region as a result of charge in the charge storage gate that represents the memory value. This problem is due to the stacking of a controlling gate and a charge storage gate in series with each other and above the bulk semiconductor region. In addition, conventional flash memory devices typically use an oxide-nitride-oxide (“ONO”) layer between the controlling gate and the charge storage gate. The ONO layer is difficult to fabricate because it is between two polysilicon layers that form the controlling and charge storage gates. Finally, this structure of conventional flash memory devices also suffers from difficulties in the charging and discharging of the device. In particular, the voltage drop from the controlling gate through the stored charge is significant and requires higher controlling gate voltages to affect the channel in the bulk semiconductor region.
Accordingly, there is a need for improved integrated circuit designs and improved lithographic processes, particularly for processes which can offer high precision, cost savings, improved performance, and improved transistor density. Those and other advantages of the present invention will be described in more detail herein below.